In recently years, the development of the portable telecommunications and laptop computers has become a major driving force in semiconductor IC's design and technology. One of most attractive semiconductor's merchandises is a very high-density non-volatile mask ROM. To achieve very high-density mask ROM, a novel semiconductor mask ROM technology incorporating a vertical cell is aiming at this objective and was proposed by Bertagnoili et al., in the reference, "B. Bertagnoili et al., `ROS: An Extremely High Density Mask ROM Technology Based On Vertical Transistor Cells`, Symp. on VLSI Tech. Dig., p, 58, 1996." The key of the technology is a cell concept based on a vertical MOS transistor in a trench which allows to use the bottom of the trench as additional -elf-aligned bit line, and thus to double the bit line density. The technology is enabling an approximately twofold packing density compared to conventional planar ROM.
An alternatively method to double the storage capacity is using a novel multi-state (.gtoreq.3 kinds of state) concept. Such a memory cell can double the storage capacities without increasing chip area. For example, if memory cells store only data "0" and "1 " states, a more great number of mask ROM cell transistors should be demanded to provide storage data as compare with that of memory cells which can store four kind of states, called multiple state mask ROM cells.
A conventional multi-value ROM stores with more than three states, in the manner that changes the threshold voltage of memory cell transistors is given by Sheng et al., in U.S. Pat. No. 5585,297 issued on Dec. 17, 1996. A plurality of ion implantation stages using boron ions is performed incorporating with using a plurality of different mask patterns and different dosage level. However, the high dose boron coding implant will result in a lower junction breakdown performance of the coded MOSFET and a very high band-to band leakage current between the adjacent cells as is stated in the reference "U.S. Pat. No.5,683,925, to Irani et al., issued on Nov. 4, 1997." Hence, Irani et al., in their patent proposed a method of fabricating the mask ROM to solve above issues. In the method, a thick gate oxide layer 18 is thermally grown within ROM array area 30, even the gate oxide 2 in the periphery 32 is thinner, as shown in FIG. 1.
An alternative method is proposed by Takiziawa et al., in U.S. Pat. No. 5,556,800 issued on Sep. 17 (1996)." Takiziawa et al., on the contrary, in the manner that varies the gate insulating layer's thickness to change the threshold voltage of channel region. The channel region is divided into dual parts; one divided part having a different gate oxide thickness from the other, and thus a different transitivity for ion implant. Namely, the gate electrode has different characteristics of a drain current corresponding to a gate voltage (I.sub.D -V.sub.G) in the channel regions adjacent to each other.